An Innovative Successive Approximation Register Analog-to-Digital Converter for a Nine-Axis Sensing System

With nine-axis sensing systems in 5G smartphones, mobile power consumption has become increasingly important, and ultra-low-power (ULP) sensor circuits can decrease to tens of microwatts. This paper presents an innovative successive approximation register analog-to-digital converter, which comprises fine (three most significant bits (MSBs) plus course conversion (11 least (LSBs)) capacitive digital-to-analog converters (CDACs), ULP, four-mode reconfigurable resolution (9, 10, 11, or 12 bits), internally generated clock, meta-detection, the switching base midpoint voltage (Vm) (SW-B-M), bit control logic, multi-phase MSBs) LSBs) switch phase input signal negative (VI + NEG) generator. Then, mechanism discrete Fourier transform (DFT)-based calibration is applied. The scalable technique was used, analog/digital Vanalog (1.5 V) Vdigital (0.9 meet specifications ULP system. CDACs reconfigure resolutions, 9–12 bits, for use applications. corresponding dynamic signal-to-noise distortion ratio performance 50.78, 58.53, 62.42, 66.51 dB. In 12-bit mode, ADC approximately 2.7 μW, figure merit (FoM) 30.5 fJ each step.